1. Field of the Invention
The present invention is related to an arrangement for deriving a byte clock from a serial, packet-oriented transmission data bit stream of a ring-shaped network comprising an extremely high data transmission rate, as well as for the synchronization of the derived byte clock with an internal processing clock of a terminal equipment connected to the ring-shaped network, whereby at least one filler information comprising the same binary information at all bit positions is inserted into the data stream between the data packets, each provided with a start of a data packet information, and the conversion of the serial data stream into a byte sequence adapted to the internal processing speed occurs in a series-to-parallel converter clocked by a data bit clock derived from the data bit stream.
2. Description of the Prior Art
The recognition and synchronization methods known in packet-oriented data transmission or, respectively, data multiplex technology, serve for the recognition of the beginning of a packet and, therefore, of the packet byte clock as well, and serve for the synchronization of this byte clock with an internal byte processing clock employed in a terminal equipment. The serial, packet-oriented transmitted data are thereby read into a series-to-parallel converter, usually realized by a shift register, and the data present at the parallel outputs of the shift register are investigated for the presences of a start packet bit information. At the time such a bit combination appears, the data are read from the shift register into a register integrated in terminal equipment and the byte or, respectively, processing clock inherent in the terminal equipment is adapted to the packet byte clock derived from the start of packet information. Due to the immediate synchronization of the two byte clocks, both shortenings and lengthenings of the byte clock pulses inherent in the terminal equipment occur. A shortening of the byte clock pulse inherent in the terminal equipment means a brief increase of the byte clock or, respectively, processing speed in the terminal equipment, whereby the admissible limit processing rate of the following circuit technology ios exceeded, particularly given extremely high data transmission rates in ring-shaped networks, even given a very fast circuit technology, and considerable disturbances are produced in the further processing, byte-clock clocked system components of the terminal equipment.